This application claims the benefit of priority under 35 U.S.C. xc2xa7119(a) of Korean Patent Application No. 2000-32390 filed on Jun. 13, 2000. A certified copy of the Korean Patent Application is submitted concurrently herewith.
1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly, a semiconductor memory device having a voltage stabilization circuit that is capable of stabilizing a boosted voltage level.
2. Description of the Related Art
In dynamic random access memories (DRAMs), a boosted voltage, which is a voltage higher than the power supply voltage by a threshold voltage amount or higher, is used for controlling cell transistors. Boosted voltage is used because it takes a relatively long time to transmit the charge stored in a cell capacitor to the bit line, and to transmit a sufficient voltage of a bit line to a cell capacitor while storing data. Therefore, a boosted voltage generation circuit is one of the essential circuits in a DRAM.
During the operation of a memory formed of silicon, a boosted voltage Vpp depends on the number of circuits, the amount of charge used by each circuit, and the performance of each circuit in compensating for the amount of charge that is used. Circuits used for generating the boosted voltage Vpp include a boosted voltage Vpp pump and an active kicker. However, when the compensation performance of the pump and active kicker are fixed, the level of boosted voltage Vpp changes or fluctuates. In other words, in a case where a small amount of boosted voltage Vpp is used, the level of the boosted voltage Vpp increases when the amount of charge compensated for is larger than the amount of boosted voltage Vpp used. In contrast, in a case where a large amount of boosted voltage Vpp is used, the level of boosted voltage Vpp decreases when the amount of charge compensated for is smaller than the amount of the boosted voltage Vpp used.
When a memory cell array comprised of block units is activated in a DRAM, a boosted voltage Vpp load varies depending on the position of the block unit in the cell array. The load varies depending on whether a block unit located near the edge (e.g., outer) of the cell array is selected, or a block unit located in the interior (e.g., inside) of the cell array is selected. For example, for a memory device comprised of four cell array blocks, depending on the location of the activated cell array block, the maximum amount of boosted voltage Vpp used (e.g., the maximum amount of charge consumption) can be twice as large as the minimum amount of charge consumption.
FIG. 1 illustrates a main path through which a boosted voltage Vpp is applied when a row address strobe (RAS) is active in a conventional DRAM. Reference numerals 10 and 11 designate a first cell array block and a second cell array block, respectively. Reference numerals 14 and 16 designate selection control signal Pxi drivers used in selecting a cell array block. Reference numeral 12 denotes a broken line, which designates an output line of selection control signal Pxi driver 14. Reference numeral 13 denotes a thick solid line, which designates an output line of selection control signal Pxi driver 16.
Signals Px0a and Px2a can be used to select selection control Pxi drivers 14 and 16, respectively, and are generated based on an address. The selected selection control signal Pxi driver (e.g., selection control signal Pxi driver 14 or selection control signal Pxi driver 16) outputs a boosted voltage Vpp to a word line through a sub-word line driver 15, 17, or 18. The structure and operation of selection control signal Pxi drivers 14 and 16, and sub-word line drivers 15, 17, and 18 are apparent to those skilled in the art, and thus, further descriptions of the components are not provided.
DRAMs are designed such that two adjacent cell array blocks share a control signal Pxi driver and an output line. For example, as depicted in FIG. 1, two adjacent cell array blocks, first cell array block 10 and second cell array block 11, share selection control signal Pxi driver 16 and output line 13. However, selection control signal Pxi driver 14, located at the edge of the memory cell array, and output line 12 are used only by first cell array block 10, which is located at the edge. Accordingly, the length or load of output line 12 of selection control signal Pxi driver 14 is approximately one-half the length or load of output line 13 of selection control signal Pxi driver 16.
During the DRAM""s operation, the discrepancy in the length of the output lines cause the amount of boosted voltage Vpp used by selection control signal Pxi driver 14 and output line 12, which are located at the edge of the memory cell array, to be approximately one-half of the amount of boosted voltage Vpp used by selection control signal Pxi driver 16 and output line 13, which are shared by two adjacent cell array blocks. The differing amount of boosted voltage Vpp used causes the boosted voltage Vpp level to fluctuate during the DRAM""s operation. In DRAMs, fluctuating boosted voltage Vpp levels are undesirable.
FIG. 2 illustrates a diagram that explains the different amounts of boosted voltage used during a precharge in a conventional DRAM. Reference numerals 20, 21, 22, and 23 designate a first through fourth cell array block, respectively. Reference numerals 24, 25, and 26 designate shared sense amplifiers, where each shared sense amplifier is shared by two adjacent cell array blocks, Reference numerals 27, 28, 29, 30, 31, and 32 designate isolation transistor units.
As depicted in FIG. 2, in a memory device using a shared sense amplifier, a bit line of an inner cell array block, for example, second cell array block 21, is sensed by two shared sense amplifiers 24 and 25. Shared sense amplifier 24 is positioned along the upper side of second cell array block 21 and shared sense amplifier 25 is positioned along the lower side of second cell array block 21. In contrast, a bit line of an outer or edge cell array block, for example, first cell array block 20, is sensed by a single shared sense amplifier 24.
When sensing a bit line of one of two adjacent cell array blocks, the isolation transistor unit corresponding to the bit line of the cell array block that is not being sensed is turned off, effectively blocking the bit line from the shared sense amplifier. For example, when sensing a bit line of an outer cell array block (e.g., first cell array block 20), isolation transistor unit 28 is turned off to block a bit line of adjacent second cell array block 21 from shared sense amplifier 24. As another example, when sensing a bit line of an inner cell array block (e.g., second cell array block 21), isolation transistor unit 27 is turned off to block a bit line of adjacent first cell array block 20, and isolation transistor unit 30 is turned off to block a bit line of adjacent third cell array block 22.
During a precharge, which typically occurs after RAS becomes active, a blocked bit line is reconnected to a shared sense amplifier. Boosted voltage Vpp is used to reconnect a blocked bit line. For an outer cell array block, a bit line of one adjacent cell array block is reconnected to a shared sense amplifier during the precharge. For an inner cell array block, two bit lines, one from each adjacent cell array block, are connected to its respective shared sense amplifier during the precharge. The amount of boosted voltage Vpp used during the precharge is proportional to the number of bit lines reconnected during the precharge. Accordingly, during precharge, the amount of boosted voltage Vpp used in an outer cell array block is approximately one-half the amount of boosted voltage Vpp used in an inner cell array block.
In conventional semiconductor memory devices having shared circuits to reduce the size of a cell array block, the amount of boosted voltage Vpp used varies depending on the location of the activated cell array block. The boosted voltage Vpp amount or level fluctuates depending on the activated cell array block""s location. Boosted voltage Vpp level fluctuations are undesirable because they tend to reduce the life span of the memory device and/or deteriorate the operating characteristics of the circuit.
An object of the present invention is to provide a boosted voltage stabilization circuit that is capable of stabilizing the boosted voltage level for use in semiconductor memory devices.
For purposes of summarizing the invention, certain aspects, advantages, and novel features of the invention have been described herein. It is to be understood that not necessarily all such advantages may be achieved in accordance with any one particular embodiment of the invention. Thus, the invention may be embodied or carried out in a manner that achieves or optimizes one advantage or group of advantages as taught herein without necessarily achieving other advantages as may be taught or suggested herein.
In one embodiment, a semiconductor memory device includes a cell array and a boosted voltage stabilization circuit. The cell array includes a plurality of memory cell array blocks sharing a predetermined circuit, wherein the predetermined circuit is operable to use a boosted voltage higher than a power supply voltage. The boosted voltage stabilization circuit includes an additional load, wherein the additional load is coupled to the boosted voltage when a memory cell array block at an edge of the cell array is selected.
In another embodiment, a semiconductor memory device includes a cell array and a boosted voltage stabilization circuit. The cell array includes one or more memory cell array blocks sharing a predetermined circuit, wherein the predetermined circuit is operable to use a boosted voltage higher than a power supply voltage. The boosted voltage stabilization circuit is operable for driving a predetermined circuit of an unselected memory cell array block at one edge of the cell array as a load when a signal indicating selection or non-selection of a memory cell array block at the other edge is activated.
In still another embodiment, a semiconductor memory device includes a cell array, a selection line, a boosted voltage line, and a boosted voltage stabilization circuit. The cell array includes one or more memory cell array blocks. The selection line is coupled to the cell array, and the selection line is operable to carry a signal indicating the selection of an a memory cell array block at an edge of the cell array. The boosted voltage line carrying a boosted voltage is coupled to the cell array. The boosted voltage stabilization circuit is coupled to the selection line, and the boosted voltage stabilization circuit includes an additional load, wherein the additional load is coupled to the boosted voltage line in response to detecting the signal on the selection line.
In yet another embodiment, a semiconductor memory device includes a boosted voltage line and a discharge circuit, wherein the boosted voltage line is coupled to a boosted voltage. The discharge circuit includes an additional load, and the discharge circuit is operable to couple the additional load to the boosted voltage line in a first state, and the discharge circuit is further operable to de-couple the additional load from the boosted voltage line in a second state.
In a further embodiment, in a semiconductor memory device, a method for facilitating the use of a uniform boosted voltage includes: providing a cell array having one or more memory cell array blocks; providing a boosted voltage line carrying a first boosted voltage value; detecting a selection or non-selection of a memory cell array block located at an edge in the cell array; in response to detecting the selection of a memory cell array block located at an edge in the cell array, coupling a load to the boosted voltage line, the load causing the first boosted voltage value on the boosted voltage line to drop to a second boosted voltage value; and in response to detecting the non-selection of a memory cell array block located at an edge in the cell array, de-coupling the load from the boosted voltage line and discharging the load.
These and other embodiments of the present invention will also become readily apparent to those skilled in the art from the following detailed description of the embodiments having reference to the attached figures, the invention not being limited to any particular embodiment(s) disclosed.